(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to reduce the roughness of a gate insulator layer, which had previously been subjected to a threshold voltage ion implantation procedure.
(2) Description of Prior Art
The desired threshold voltage, for both N channel, (NMOS), as well as P channel, (PMOS), metal oxide semiconductor devices, are usually accomplished via ion implantation procedures, performed through a gate insulator layer into the channel region of the complimentary metal oxide semiconductor, (CMOS), device. These implantation procedures, usually performed through a silicon oxide gate insulator layer, using boron or BF.sub.2 ions, for both the NMOS and PMOS devices, can however result in an increase in the roughness of the surface of a silicon oxide gate insulator layer. The increase in surface roughness of the gate insulator layer negatively influences the coatablity of overlying photoresist layers, used to define subsequent device features.
This invention will teach a novel procedure used to restore the topography, or surface roughness of a silicon oxide gate insulator layer, which had been subjected to a boron type, threshold adjust, ion implantation procedure. Prior art, such as Gdula et al, in U.S. Pat. No. 3,925,107, describe a post-oxidation, anneal process which reduces the fixed charge, and fast states, in silicon dioxide, gate layers as thin as 100 Angstroms. However that prior art does address the novel process, now presented, allowing reductions in the surface roughness of the thin silicon oxide gate insulator layers, after the surface roughness of the gate insulator layer was increased as a result of being subjected to a threshold adjust implantation procedure.